48K ram

The Upper ram

To provide 48K, the top 32K needs to be populated. In the original spectrum, this was done using 32k x1 Ram chips and decoding logic. However, Sram is cheap, so these days, it makes much more sense to use that instead. There are however, two options for SRAM, Simply providing the extra 32K can be done using a 32K SRAM chip and one decoding chip. (with /CS = A15+/MemRq)

The method i chose however, was to use a 128K SRAM chip and some additional decoding to provide the basic 128K memory map. At this stage, i am not providing the required port at $7FFD, The Bank select bits are wired to 0, making the first page appear at $C000 In addition, the Ram will also respond at $4000, so writes to this will appear in Page 5, similar to on the 128K spectrum. (And page 2 will appear at $8000 as well)

Theory

The theory of this circuit is quite simple. The Ram chip provides 128K x8 of ram. We are dealing with it in 8 pages (Although were only using three of them at this stage)

The 74LS138 provides an active low output for each bank,

• $0000-$3FFF (unused)
• $4000-$7FFF (We want bank 5 in there)
• $8000-$CFFF (We want bank 2 in there)
• $D000-$FFFF (Currently bank 0)

TO control the bank we want on the bus, we use the A14-A16 lines of the Ram chip.

A 74LS157 is used to swap in either $000 or another value ($101 or $010 depending on the state of Q2 on the '138)

The CS logic is simply /CS = Q1+Q2+A3, so if any of them go low, CS goes low as well. This is implemented using a 74LS10 gate (NAND) followed by another one to invert the input for AND.

So, A14,15,16 are as follows for each output of the 138.

• Q0 - (CS is high so N/A)
• Q1 - $010
• Q2 - $101
• Q3 - $000 (*)

(*) Technically the values on A0-A2, this is unimportant here, but will become important when 128K paging is implemented.

In this configuration, the ULA Ram simply acts as a shadow for this Ram chip when we write to $4000-$7FFF. Because the ULA ram is resistor coupled, they can both be active at the same time, and the CPU will write to both Ram chips, although the CPU will read from the 128K ram chip. The ULA ram is still required however because the ULA does not have access to the new 128K ram chip.

Also, another thing that is missing is contention when the CPU writes to bank 5 when it is pages into $C000. For 48K, this is unimportant, but again, will need to be addressed once 128K paging is considered.

Schematic

This design bears no resembelence to the original 48K schematic.

Finished product

Testing

The initial test is to plug the board in and turn the computer on.

Enter the command:

 PRINT PEEK 23731   ("P" (Capt+symbol shift) "O" 23731 [enter])

You should get the figure "255", this means all the 48K of memory is working.

If you get the figure: "127", the board is not working at all.